This invention relates to integrated circuits and, more particularly, to performing sequential equivalence checking aware register retiming of an integrated circuit design.
Every transition from one technology node to the next technology node has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit of integrated circuit area. Synchronous integrated circuits have further benefited from this development as evidenced by reduced interconnect and cell delays, which have led to performance increases.
To further increase the performance, solutions such as register retiming have been proposed, where registers are moved among portions of combinational logic, thereby achieving a more balanced distribution of delays between registers and thus potentially a higher clock frequency at which the integrated circuit may be operated.
However, performing register retiming may be complicated and error prone, especially when different portions of the integrated circuit operate in different clock domains and registers have different clocks, clock polarity, or particular reset, preset, or initialization constraints. Verifying that the pre-register retiming circuit design has the same behavior as the post-register retiming circuit design is desirable.